Semiconductor processing involves forming transistors on wafers. A transistor typically includes a gate dielectric and a gate electrode, a source and a drain, and a channel region between the source and the drain. In Complimentary Metal Oxide Semiconductor (CMOS) technology, transistors may typically be of two types: Negative Channel Metal Oxide Semiconductor (NMOS) and Positive Channel Metal Oxide Semiconductor (PMOS) transistors. The transistors and other devices may be interconnected to form integrated circuits (ICs) which perform numerous useful functions.
The speed of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) depends primarily on electron—in the case of NMOS—or hole—in the case of PMOS—mobility in the channel region between the source and the drain. In general, mobility is a measure of hole or electron scattering in a semiconductor. Increasing mobility can have a profound benefit for digital electronic devices allowing faster switching and lower power consumption. Therefore, methods of increasing electron and hole mobility in transistors have been a major focus.
One solution to increase transistor speed is to strain the silicon in the channel. Compressing the channel region in PMOS transistors is particularly important because hole mobility in PMOS transistors is much less than electron mobility in NMOS transistors due to the higher effective mass of holes.
Compressing the silicon lattice distorts its physical symmetry as well as its electronic symmetry. The lowest energy level of the conduction band is split, with two of the six original states dropping to a lower energy level and four rising to a higher energy level. This renders it more difficult for the holes to be ‘scattered’ between the lowest energy states by a phonon, because there are only two states to occupy. Whenever holes scatter, their motion is randomized. Reducing scatter increases the average distance a hole can travel before it is knocked off course, increasing its average velocity in the conduction direction. Also, distorting the lattice through compressive strain can distort the hole-lattice interaction in a way that reduces the hole's effective mass, a measure of how much it will accelerate in a given field. As a result, hole transport properties, like mobility and velocity, are improved and channel drive current for a given device design is increased in a strained silicon channel, leading to improved transistor performance.
Compressive nitrides have been used to improve performance of PMOS transistors. For example, silicone nitride (SiN) combined with hydrogen atoms have been reported to reach compressive stresses of close to 3 GPa. Note that compressive stress is presented as an absolute value that simplifies comparison of this property for various films. In general, controlling N—H, Si—H, and Si—N bond ratios currently allows developing films with up to 3.0 GPa compressive stress. However, compressive nitrides still can not meet requirements of future transistor generations where higher hole mobility (i.e. more compression in the channel region) are needed. Moreover, many compressive nitrides require annealing at elevated temperatures for prolonged time significantly impacting thermal budgets of transistors.
Silicone Germanium (SiGe) has also been used to strain the channel region. SiGe can be grown as an epitaxial layer into pre-etched silicon-based source and drain regions. Since SiGe lattice is larger than silicon lattice by about 4%, compressive stress is created in the channel regions. Compressive stresses of approximately 1 GPa have been reported, resulting in a 35% increase in current flow in PMOS transistors. However, because strain builds up asymmetrically in a SiG/Si stack, the maximum permissible stack height is typically no more than 50 nm limiting the overall stress level.
Amorphous carbon exhibit many attractive properties for thin film applications in semiconductors and other devices. (F. Piazza et al, Diamond Relat. Mater. 14, 994-999 (2005); B. Kleinsorge et al, Diamond Relat. Mater. 7, 472-476 (1998)). One such property is post-deposition residual compressive stress that can be used to strain the channel in PMOS transistor architecture. However, available deposition methods require high ion energy, such as 100 eV and above, that may be damaging to device. Bailey et al. (U.S. Pat. No. 5,470,661) and Neuberger et al. (U.S. Pat. No. 5,965,216) disclosed low temperature deposition of amorphous carbon films (also referred to as a diamond-like carbon (DLC) film) using plasma-enhanced chemical vapor deposition from hydrocarbon/helium plasma. The method disclosed using an acetylene precursor diluted in helium resulting in 1.5 GPa compressive films. Such compressive stresses are not sufficient for new generation transistors.
Overall, higher compressive stresses, especially higher than 3.0 GPa and using regular PECVD with low ion energy such as 1-3 eV are desired for PMOS transistors. Accordingly, new transistor architectures and fabrication processes for generating channel strain are needed.